Ataberk's Research | Ataberk Olgun

I am interested in the intersection between computer architecture and memory system reliability and performance, including:

Understanding the various properties of read disturbance in DRAM under different conditions and access patterns.
Developing effective, high-performance, low-cost solutions that comprehensively mitigate read disturbance in DRAM.
Uncovering new computational functionality in real DRAM chips to enable low-cost processing-in-memory architectures.

Read Disturbance in DRAM

Illustration yanked from https://hackaday.com/2015/03/13/creative-dram-abuse-with-rowhammer

DRAM is the dominant technology used for main memory in almost all computing systems due to its low latency and low cost per bit. Modern DRAM chips suffer from read disturbance. RowHammer and RowPress are two widespread DRAM read disturbance phenomena. Repeatedly accessing (i.e., hammering) a row or keeping a row open for a very long time (i.e., pressing) induces bitflips in physically nearby DRAM rows.

O. Mutlu, A. Olgun, and A. G. Yağlıkcı, “Fundamentally Understanding and Solving RowHammer,” in ASP-DAC, 2023.

Understanding DRAM Read Disturbance

There is still a lot we do not know about RowHammer (or DRAM read disturbance, in general), its properties/sensitivities, and the manifestations of such properties in cutting-edge and future DRAM chips. It is critical to fundamentally understand the various properties of RowHammer under different conditions and access patterns, in order to develop fully-secure and efficient solutions.

Here is a list of my recent work that furthered the understanding of DRAM read disturbance via experimental analyses on real DRAM chips:

A. Olgun et al., “Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance,” in HPCA, 2025.
A. Olgun et al., “Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips,” in DSN, 2024.
A. Olgun et al., “An Experimental Analysis of RowHammer in HBM2 DRAM Chips,” in DSN Disrupt, 2023.
A. Olgun et al., “DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips,” IEEE TCAD, 2023.
H. Luo, I. E. Yüksel, A. Olgun, A. G. Yaglikçi, and O. Mutlu, “Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies,” in VTS, 2025.
I. E. Yuksel, A. Olgun, N. Bostanci, H. Luo, A. G. Yaglikçi, and O. Mutlu, “ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems,” in MICRO, 2025.
I. E. Yuksel et al., “PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips,” in ISCA, 2025.
Y. C. Tugrul et al., “Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions,” in HPCA, 2025.
G. Yaglikci et al., “Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions,” in HPCA, 2024.
L. Orosa et al., “SpyHammer: Understanding and Exploiting RowHammer under Fine-Grained Temperature Variations,” IEEE Access, 2024.
H. Luo et al., “RowPress: Amplifying Read Disturbance in Modern DRAM Chips,” in ISCA, 2023.
A. G. Yağlıkçı et al., “Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices,” in DSN, 2022.

Solving DRAM Read Disturbance

As the RowHammer vulnerability (or DRAM read disturbance, in general) worsens with DRAM technology scaling, developing extremely efficient and fully secure RowHammer solutions becomes increasingly important. Even though many prior works develop various software- and hardware- level RowHammer solutions, these solutions incur non-negligible and increasingly more significant system performance, energy, and hardware area overheads as RowHammer vulnerability worsens.

Here is a list of my recent work that developed efficient architectural techniques to prevent read disturbance bitflips:

A. Olgun et al., “ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation,” in USENIX Security, 2024.
F. N. Bostanci et al., “Understanding and Mitigating Covert Channel and Side Channel Vulnerabilities Introduced by RowHammer Defenses,” in MICRO, 2025.
O. Canpolat et al., “Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance,” in HPCA, 2025.
O. Canpolat et al., “BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads,” in MICRO, 2024.
H. Hassan, A. Olgun, A. G. Yaglikci, H. Luo, and O. Mutlu, “Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient in-DRAM Operations,” in MICRO, 2024.
N. Bostanci et al., “CoMeT: Count-Min Sketch-based Row Tracking to Mitigate RowHammer with Low Cost,” in HPCA, 2024.
A. G. Yağlikçi et al., “Blockhammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows,” in HPCA, 2021.